1. Technical Field
The present invention relates to a power semiconductor device such as a semiconductor rectifier element (hereinafter referred to as a diode) and IGBT (Insulated Gate Bipolar Transistor).
2. Related Art
In recent years, various power converters including inverters are utilized in the field of power electronics. An inverter has a freewheeling diode (FWD) for power connected in anti-parallel with a switching element such as IGBT. For making the frequency of the inverter higher, the performance improvement of the FWD along with the performance improvement of the switching element is important.
FIG. 11 is a cross-sectional view showing the structure of a conventional typical freewheeling diode for power. The power diode is a diode comprising a p-intrinsic-n-type (pin-type) structure and it maintains a high voltage in a highly resistive intrinsic layer (i layer). This i layer is also referred to as an n− drift layer 62. The power diode having a rated voltage of 600V or more uses a wafer which is cut out from an ingot of silicon, etc., so an n-type semiconductor substrate (wafer) constitutes an n−-drift layer 62. A p-anode layer 63 is formed on one surface side of the n− drift layer 62. An anode electrode 65 which passes a main current is connected on surface 64 of this p-anode layer 63. The p-anode layer 63 and the anode electrode 65 pass the main current, so they are referred to as active regions. On the one hand, a p+-guard ring 71 and a field plate electrode 72 connecting to the p+ guard ring 71 are formed so as to surround this p-anode layer 63. Additionally, in an outer circumference end of a chip of the diode, a p-type or n-type channel stopper layer 73 and a stopper electrode 74 connecting to the channel stopper layer 73 are formed. As above, the portion surrounding the outer circumference of the active region is the region for relaxing an electric field when a reverse bias voltage is applied on the diode and is referred to as an edge termination region. An interlayer insulating film 68 is formed in a portion of the surface of the diode. The interlayer insulating film 68 protects the semiconductor surface such that the semiconductor surface is not exposed. Although not further depicted in the figures, a protective film for protecting the surface such as a polyimide film or a silicon oxide film is also formed. On another surface of the n−-drift layer 62, n-field stop layer 67 with a higher concentration than that of the n−-drift layer 62 is formed. This n-field stop layer 67 comprises a function for inhibiting the spreading of the depletion region. Additionally, an n+-cathode 61 is formed to make contact also with the n-field stop layer 67 on another surface of the semiconductor substrate. A cathode electrode 66 is formed such that it connects with the n+-cathode 61.
As the performance improvement of FWD, a soft recovery due to a reduction in a reverse recovery peak current (Irp), which is a peak value of a reverse recovery current (Irr), is included in addition to a loss reduction due to reductions in a forward voltage (Vf) and a reverse recovery charge (Qrr). The reverse recovery peak current (Irp) can be reduced by lowering an injection efficiency of the anode. FIG. 3, etc. of Patent Document 1 shows a diode comprising a structure referred to as MPS (Merged Pin Schottky). The diode suppresses the injection of holes from the anode and achieves the soft recovery while suppressing an increase of leak current by establishing a Schottky junction and pn junction jointly. In the diode of pin structure, a similar effect can be obtained also by simply lowering the concentration of the p-type anode layer. For example, the technique for forming a defect layer having many lattice defects in the outermost surface of the p-type anode layer and reducing the injection efficiency in a diode with the pin structure is described in FIG. 1, etc. of Patent Document 2.
Also, the injection efficiency of the anode can be lowered to achieve the soft recovery as well by decreasing selectively the lifetime of the anode side of the n-type drift layer by putting the light ions such as helium and proton on the surface side.
Additionally, in FIG. 1, etc. of Patent Document 3, a diode of the pin structure with a natural oxide film placed between a p-type polysilicon layer (corresponding to the p-type anode layer) and an n−-type semiconductor layer (corresponding to the drift layer) is described.
However, if a concentration of the anode layer is extremely lowered in the pin diode, there is a risk that the p-layer becomes depleted when a high voltage is applied and punches through the anode electrode and the leak current increases. Also, even if designing the pin diode not to cause the above punch-through does not occur, the tolerance for external disturbances such as a defect in a process and a microcrack at the time of assembling decreases.
Also, if a local lifetime control was performed by the irradiation of light ions, there is similarly a risk in which the leak current increases, and there exits an issue which leads to an increase in the cost of elements, because irradiation facilities are very expensive.
Additionally, in case of the diode described in Patent Document 3, the strongest electric field is generated in a natural oxide film between the p-type polysilicon layer and the n−-type semiconductor layer as a reverse bias voltage is applied, so the possibility that the natural oxide film results in breakdown becomes high. (Prior art documents)